# Problem Set 1
Source: [DL_P1.pdf](https://www.realdigital.org/downloads/2a82eeae9b4e078c636f267642cc6c3c.pdf) Revision: 2/3/19
```{warning}
[The overline symbol (A̅) may be hidden in Firefox if the default zoom level is used](https://bugzilla.mozilla.org/show_bug.cgi?id=1741887). The symbol below should have an overline like A̅. De- or increase the zoom level if you encounter any Boolean equations.
$ \overline A $
```
## 1
### 1.1
When the pushbutton SW1 is not pressed, what is the voltage at $V_A$?
---
Ground
### 1.2
When the SW1 is pressed, what is the voltage at $V_A$?
---
3.3V
### 1.3
When the SW1 is pressed, what current flows in the 1K resistor $R_A$?
---
$3.3V / 1kΩ = 3.3mA$
### 1.4
When SW1 is pressed, what power is dissipated in $R_{A}$?
---
$ U^2 / R = (3.3V)^2 / 1kΩ$
### 1.5
In the LED circuit, 1.3V is required at $V_B$ to forward-bias the LED and cause current to flow. Given there is a 1.3V drop across the LED, what resistance $R_B$ is required for 20mA to flow through the LED?
---
Voltage drop on $R_B$ will be $2V$. $R_B = 2V / 20mA = 100Ω$
### 1.6
What power is dissipated in the LED?
---
$P = U \cdot I = 1.3V \cdot 20 mA = 26 mW$
### 1.7
In the circuit on the far right, if $R_C$ dissipates 25mW, what is $V_C$?
---
$ 25mW = P_{Rc} = U^2 / R_{c} \Rightarrow U = \sqrt{P \cdot R} = 5V $
### 1.8
Using the $V_C$ voltage you calculated, if $R_C$ is changed to 100Ohms, how much power would it dissipate?
---
$ P = U^2 / R = 250 mW $
In other words, if the voltage stays the same but the resistance is reduced to 0.1 fold, then the energy will be 10 fold.
### 1.9
Using the $V_{C}$ voltage you calculated and a 1K $R_{C}$, if pressing SW2 causes the total circuit power to increase to 75mW, what value must $R_{D}$ be?
---
There are two solutions, one of them is based on [Superposition principle](https://en.wikipedia.org/wiki/Superposition_principle) the second one by manually calculating the total resistance of parallel resistors $R_{C}$ and $R_{D}$ and deriving $R_{D}$.
According to the superposition principle the circuit can be divided into two subcircuits which act individually
1. $V_{C}$ and $R_{C}$
2. $V_{C}$ and $R_{D}$
The first subcircuit consumes 25mW so the second should consume $ 75mW - 25mW = 50mW$. $R_{D} = U^2 / P = (5V)^2 / 50mW = 500Ω $. In other words, we need half of the $R_{C}$ to consume two fold power.
## 2
(2.1)=
### 2.1
The example circuit below asserts its output as a logic 0 when both switches are closed. Based on your reasoning for how this example circuit works, sketch a different circuit that asserts logic 1 when both switches are closed. Label the switches 1 and 2, and complete the truth table for your circuit. Then circle the correct term (high or low, and open or closed) to complete the following sentences describing the AND and OR relationships for your circuit:
AND Relationship:
The output F is [high / low] when SW1 is [open / closed], and SW2 is [open / closed].
OR Relationship:
The output F is [high / low] when SW1 is [open / closed], or SW2 is [open / closed]
---
In the example, the output `F` is right below the resistor. This allows the resistor to be high as long as the switches are not both closed. The magic happens through the resistor. If there is connection between $V_{dd}$ and ground, then no current flows. Without current there is nothing that the resistor can resist, so there is no voltage drop on the resistor. In other words the resistor acts like a wire.
If `F` should be 1 when both switches are closed, then we can move `F` to the top of ground. Then `F` will be 0 if the two switches are open. With both switches connected, `F` will be still at ground level because there is nothing between `F` and ground that can cause a voltage difference. So what did we forget?
We have to move the resistor between `F` and ground to create this voltage drop. Then we have a similar behavior described above.
Truth table:
| SW1 | SW2 | F |
|-----|-----|---|
| closed | closed | h |
| closed | open | l |
| open | closed | l |
| open | open | l |
AND Relationship:
The output F is [**high** / low] when SW1 is [open / **closed**], and SW2 is [open / **closed**].
OR Relationship:
The output F is [high / **low**] when SW1 is [**open** / closed], or SW2 is [**open** / closed]
Note:
- *AND* implies *both* or in general *every*.
- *OR* implies *one of them* or *either*
### 2.2
The example circuit below asserts its output as a logic 1 when either switch is closed. Sketch a new circuit that asserts logic 0 whenever one or both switches are closed. Label the switches 1 and 2, and complete the truth table below. Circle the correct term (high or low, and open or closed) to complete the following sentences describing the AND and OR relationships for your circuit:
AND Relationship:
The output F is [high / low] when SW1 is [open / closed], and SW2 is [open / closed].
OR Relationship:
The output F is [high / low] when SW1 is [open / closed], or SW2 is [open / closed].
---
In the example {ref}`2.1` the resistors were in series which allows them to close the circuit if both *agree*, in other words, if there is *consensus*. If we want to give each switch the ability to close individually, then we can connect them in parallel like in this example.
We want to output ground (0V) if either of the switches close. We can modify the circuit the same way as we did in {ref}`2.1` by moving the resistor right below the $V_{dd}$ and `F` below the resistor.
Truth table:
| SW1 | SW2 | F |
|-----|-----|---|
| closed | closed | l |
| closed | open | l |
| open | closed | l |
| open | open | h |
AND Relationship:
The output F is [**high** / low] when SW1 is [*open* / closed], and SW2 is [**open** / closed].
OR Relationship:
The output F is [high / **low**] when SW1 is [open / **closed**], or SW2 is [open / **closed**].
## 3
Complete the following:
A PFET turns [ ON / OFF ] with LLV and conducts [ LHV / LLV ] well (circle one in each bracket).
An NFET turns [ ON / OFF ] with LLV and conducts [ LHV / LLV ] well (circle one in each bracket).
---
```{note}
`PFET` and `NFET` are introduced in [Introduction to CMOS Technology (Project 2)](https://www.realdigital.org/doc/f5277015db0e08b6101744e08d5b67cb)
The author probably make a mistake in the reorganization of the problem sets. In the previous version of his book, the terms `LLV`, `LHV` etc are already introduced in the [first module – Introduction to Electronic Circuits](https://learn.digilentinc.com/Classroom/RealDigital/M1/RealDigital_Module_1.pdf):
> In a digital circuit, power supply voltage levels are constrained to two distinct values – “logic high
voltage” (called LHV or Vdd) and “logic low voltage” (called LLV or GND).
```
A PFET turns [ **ON** / OFF ] with LLV and conducts [ **LHV** / LLV ] well (circle one in each bracket).
An NFET turns [ ON / **OFF** ] with LLV and conducts [ LHV / **LLV** ] well (circle one in each bracket).
If you are new to CMOS, then you can memorize them as follows:
1. `NFET` is our base component. An `NFET` typically attaches itself to the ground (or to another transistor which is attached to the ground) with its *source*. It has a *gate* which can be opened or closed by applying a voltage. This voltage is applied between *source* and *gate*. If the voltage is high, then the gate opens and connects source with drain. Using this mechanism we can connect the *drain* to the ground or isolate it.
2. `PFET` attaches itself to the high voltage. The principle is similar to `NFET`, but now to open the gate we have to apply a voltage lower than the high voltage.
`NFET` or `PFET` is active (gate is open) if there is a voltage drop between source and drain.
```{Note}
We said that if the transistors close, there is no connection between source and drain. In reality there is a high resistance between them, a tiny amount of current can still flow. This makes NFET drive a *weak* logic high when the gate voltage is low. The same principle applies to PFET.
In summary. NFET is used for transferring *strong logic 0*, but *weak logic 1*. In other words, an NFET can draw a high current when it transfers a logical low. For PFET it is vice versa. To use the output of a logical circuit in other logical circuits we have to be able to drive high currents that is again used to drive the gates of other transistors. To create both a strong logic 1 and 0 we have to intertwine the individual strengths of NFET and PFET. We attach NFETs to create a strong connection to the logical low and PFETs to the logical high. This is where the *complementary* in CMOS (complementary MOS) comes from.
A weak logic can be overridden by a strong logic. For example if a transistors drives to a net a weak 1 and another one a strong 0, the net will be on logic level 0. Refer to the table in {ref}`ps01.4.1` and look at F's drivers in case of $A = 0$ and $B=1$ for an example. There Q1 drives a strong 1, but Q2 drives a weak 0, so the output will be 1.
More info: [Logic Design – MOSFET pass characteristics](https://eecs.wsu.edu/~ee434/Handouts/01-Logic_Design.pdf#page=12)
```
```{Attention}
> conducts LLV (logic low voltage) well
I never heard of *conducting voltage*. *Current* is conducted or in general *electricity*. The author probably means that NFET creates a connection to the LLV and PFET to the LHV.
```
## 4
Complete the truth tables below (enter “on” or “off” under each transistor entry, and “1” or “0” for output F), and enter the gate name and schematic shapes in the tables.
---
(ps01.4.1)=
### 4.1
| A | B | Q1 | Q2 | Q3 | Q4 | F |
|---|---|-----|-----|-----|-----|---|
| 0 | 0 | on | on | off | off | 1 |
| 0 | 1 | on | off | on | off | 1 |
| 1 | 0 | off | on | off | on | 1 |
| 1 | 1 | off | off | on | on | 0 |
We see that the output is 0 *only if both* inputs are 1, otherwise the output is 1. This looks like an `AND`, but negated – a `NAND`.
Using an `AND` shape (standard way of drawing a NAND) according to [ANSI](https://en.wikipedia.org/wiki/American_National_Standards_Institute):
![ANSI NAND](https://upload.wikimedia.org/wikipedia/commons/f/f2/NAND_ANSI.svg)
Here is the [IEC](https://en.wikipedia.org/wiki/International_Electrotechnical_Commission) version:
![IEC NAND](https://upload.wikimedia.org/wikipedia/commons/d/d8/NAND_IEC.svg)
There is even a DIN version which is easier to draw, but it was deprecated in favor of the IEC 60617[^din-deprecated]:
[^din-deprecated]: [OR gate symbols – Wikipedia](https://en.wikipedia.org/wiki/OR_gate#Symbols)
![DIN NAND](https://upload.wikimedia.org/wikipedia/commons/0/01/NAND_DIN.svg)
We can also draw it using an `OR` shape by *bubble-pushing* in three steps:
- we push the bubble on the output (the negation) to the inputs
- convert the `AND` to an `OR`
- we negate the inputs
Finally we have an OR gate with negated inputs.
(ps01.4.2)=
### 4.2
| A | B | Q1 | Q2 | Q3 | Q4 | F |
|---|---|-----|-----|-----|-----|---|
| 0 | 0 | on | on | off | off | 1 |
| 0 | 1 | on | off | off | on | 0 |
| 1 | 0 | off | on | on | off | 0 |
| 1 | 1 | off | off | on | on | 0 |
Output is 0 if either A or B is 1. This looks like an `OR`, but its output is negated – a `NOR`.
![ANSI NOR](https://upload.wikimedia.org/wikipedia/commons/c/c6/NOR_ANSI_Labelled.svg)
![IEC NOR](https://upload.wikimedia.org/wikipedia/commons/6/6d/NOR_IEC.svg)
Similar to {ref}`ps01.4.1` we can push the bubble to draw the NOR in AND shape.
(ps01.4.3)=
### 4.3
| A | B | Q1 Q2 Q3 Q4 | $F_{old}$ | Q5 | Q6 | F |
|---|---|-------------------------|-----------|-----|-----|---|
| 0 | 0 | same as {ref}`ps01.4.2` | 1 | off | on | 0 |
| 0 | 1 | | 0 | off | on | 1 |
| 1 | 0 | | 0 | on | off | 1 |
| 1 | 1 | | 0 | on | on | 1 |
The last stage inverts the output. {ref}`ps01.4.2` is a NOR, so this circuits becomes an OR:
![ANSI OR – Inductiveload, Public domain, via Wikimedia Commons](https://upload.wikimedia.org/wikipedia/commons/1/16/OR_ANSI_Labelled.svg)
![IEC OR – jjbeard, Public domain, via Wikimedia Commons](https://upload.wikimedia.org/wikipedia/commons/4/42/OR_IEC.svg)
### 4.4
Similar to {ref}`ps01.4.3` but here the circuit from {ref}`ps01.4.1` is inverted. So we get an AND:
![jjbeard, Public domain, via Wikimedia Commons popular in the rest of the world](https://upload.wikimedia.org/wikipedia/commons/6/64/AND_ANSI.svg)
![https://upload.wikimedia.org/wikipedia/commons/0/0f/AND_IEC.svg](https://upload.wikimedia.org/wikipedia/commons/0/0f/AND_IEC.svg)
## 5
Complete the truth table below (enter “on” or “off” under each transistor entry, and “1” or “0” for output F). Then, provide a logic equation for the circuit in the box below.
---
| A | B | C | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | F |
|---|---|---|-----|-----|-----|-----|-----|-----|---|
| 0 | 0 | 0 | on | on | on | off | off | off | 1 |
| 0 | 0 | 1 | on | on | off | off | off | on | 0 |
| 0 | 1 | 0 | on | off | on | on | off | off | 1 |
| 0 | 1 | 1 | on | off | off | on | off | on | 0 |
| 1 | 0 | 0 | off | on | on | off | on | off | 1 |
| 1 | 0 | 1 | off | on | off | off | on | on | 0 |
| 1 | 1 | 0 | off | off | on | on | on | off | 0 |
| 1 | 1 | 1 | off | off | off | on | on | on | 0 |
An easy way to determine F is:
1. Assume that this is a CMOS circuit where the NFETs are complementary to the PFETs. We can prove that by comparing the outputs of complementary FETs:
- Q1 and Q5
- Q2 and Q4
- Q3 and Q6
In the table we see that their outputs are complementary.
Additionally the NFET network is complemented by the PFET network:
- Q4 and Q5 are connected in serial, whereas their counterpart Q2 and Q1 are connected in parallel
- Q6 is in parallel to Q4 and Q5, whereas Q3 is connected in series to Q1 and Q2.
The complementary nature will ensure that NFETs and PFETs are not driving strongly against each other.
Finally the FETs inside a network also cannot disturb each other because either can only drive a single logic level strongly. For example NFETs can only drive to 0 strongly, so if every of them drives a strong value, they cannot clash and the output value will be 0.
2. The NFET Q6 is directly connected to F, so Q6 determines F whenever Q6 drives a strong 0. Consequently F is 0 whenever Q6 is on. When Q6 is off, then F is determined by Q4 and Q5. F can be driven to a strong 0 if both Q4 and Q5 are on, so F is additionally 0 when Q4 and Q5 are on. In the rest of the cases the complementary PFET network will take over and drive a strong 1.
How do we write the equation for F? F is 0:
- when Q6 is on
- when Q4 and Q5 are on
So negated F ($\overline{F}$) will be 1 in the above cases, and 0 in the rest of the cases. These transistors are controlled by the following inputs:
- Q6, Q4, Q5 are on when C, B, A are high, respectively
So:
$ \overline{F} = C + ( B \cdot A) \Rightarrow F = \overline{C + ( B \cdot A)} $
## 6
Based on your knowledge of what a two-input NAND circuit and a two-input NOR circuit built from PFETs and NFETs look like, sketch a three-input NAND and four-input NOR circuit.
---
```{image} problem-set-01_p6.svg
:width: 1000
:height: 2000
:alt: handwritten solution
```
## 7
The picture below shows a representation of a logic gate built from FETs as it might appear to a chip designer in a CAD/layout tool. The reddish polysilicon areas labeled A and B are conductive materials that form the circuit inputs, and the yellow and green areas are “diffusion” areas that have been implanted (or doped) with materials to make them more positive or more negative than the surrounding silicon. Based on your knowledge of CMOS gate structures, answer
the following.
1. Which number points to the positive diffusion area?
2. Which number points to the negative diffusion area?
3. The dotted-line box pointed to by #3 represents what type of FET?
4. What number points to the circuit output?
5. What type of logic gate is this?
![Example silicon](problem-set-01_p7_silicon.svg)
---
1. *Positive diffusion* means that the area is doped with positive ions, so we are searching for the diffusion are for PFETs. PFETs are typically connected to the supply voltage, so `1`.
2. Similar to the last problem, NFETs are connected to the ground voltage, so `2`.
3. According to 1. $\Rightarrow$ PFET.
4. We are searching for conductors which are not connected to $V_{dd}$, ground or the inputs A and B $\Rightarrow$ `4`.
5. A CMOS gate consists of a two complementary networks, p- and NFET network. The networks themselves consist of FETs. We have to localize these FETs in the picture.
A FET consists of a gate, source and drain. In the above PFET network we see two connections to $V_{dd}$, two gate connections and one connection to the output. There must be two structures. From our experience we know that they can be either in series or parallel.
As both structures are connected to the $V_{dd}$, these must be two parallel PFETs.
What about the NFET network? This time we see a single connection to the ground, two gate connections and a single connection to the output, so there should be two gates. The doped area in the middle is the connection between two gates, so the two NFETs are connected in series.
We see that the NFET network complements the PFET which confirms our solution.
Now what type of logic gate is this? The NFET network only drives a strong 0 if both NFET transistors are on, so this is a NAND.