# Problem Set 8

Source: [DL_P8_Problem_Set_9_28_18.pdf](https://www.realdigital.org/downloads/3b13c9bb577528e9186863a2b89e00c4.pdf) Revision: n/a

## 1

Complete the timing diagram below to illustrate the behavior of the counter.

<!--TODO diagram and circuit symbol-->

---

This is a synchronous 4 bit binary counter because the counter begins at 0 and counts up to $2^4-1$. It has active high asynchronous reset and synchronous counter-enable signals.

After $2^4-1$ the counter will turn back to 0 and continue counting until the reset is active. After the cycle where the reset was active the value will be 1 and the counter will increment the counter if the counter-enable is active in the moment when the clock rises.

<!--TODO diagram -->


## 2

Complete the circuit sketch for a four-bit counter by adding the required next-state logic gates in front of the flip-flops.

<!-- TODO diagram -->

---

The truth table looks as follows:

| q0 | q1 | q2 | ... | q0n | q1n | q2n | ... |
|----|----|----|-----|-----|-----|-----|-----|
| 0  | 0  | 0  | ... | 1   | 0   | 0   | ... |
| 1  | 0  | 0  | ... | 0   | 1   | 0   | ... |
| 0  | 1  | 0  | ... | 1   | 1   | 0   | ... |
| 1  | 1  | 0  | ... | 0   | 0   | 1   | ... |
| 0  | 0  | 1  | ... | 1   | 0   | 1   | ... |
| 1  | 0  | 1  | ... | 0   | 1   | 1   | ... |
| 0  | 1  | 1  | ... | 1   | 1   | 1   | ... |
| 1  | 1  | 1  | ... | 0   | 0   | 0   | ... |

We observe:

- the least significant bit is toggled every time.
- After reset, a bit is set to 1 if all the less significant bits are set to 1. If the less significant bits are set to 1 again, then this bit is set to 0. In summary a bit is toggled if all the less significant bits are set to 1. But here we define only *when* a value should change and does not describe the next value combinationally.
- A bit only depends on the last value of itself and the bits which are less significant.
- q1n is 1 if `(q0 & ~q1) | (~q0 & q1)`. This corresponds to the exclusive-or operator `q0 ^ q1`.
- q2n is 1 if:

  ```
  ( q0 &  q1 & ~q2) |
  (~q0 & ~q1 &  q2) |
  ( q0 & ~q1 &  q2) |
  (~q0 &  q1 &  q2)
  ```

  We observe that q2 must be 0 if q0 and q1 are 1, q2 must be 1 in other conditions of q0 and q1. So either q2 is true or (q0 & q1). This corresponds to the exclusive-or operation: `(q0 & q1) ^ q2`.

We can generalize this formula for the further bits:

```verilog
process @(posedge clk) begin
assign
	q0 = 1 ^ q0;
	q1 = q0 ^ q1;
	q2 = (q0 & q1) ^ q2;
	q3 = (q0 & q1 & q2) ^ q3;
end
```