Basic Combinational Building Blocks#

The circuits in the project requirements are described in a structural way, but the the code will be written as behavioral.

Exercise 80

The circuit must be in structural form before the FPGA can be configured, but the circuit is mostly described in behavioral manner. How is the process called in which behavioral description is converted to structural?

Learning Goals#

  • Understand the design and use of multiplexers, decoders, encoders, shifters




The word comes from multi and plex. Multi means many and plex means weaved or twined. A multiplexer takes many (multi) inputs and combines them (plex) into a single signal.

In our context the multiplexer does not necessarily combines all inputs all the time similar to a serializer, but selects one of them dependent on the select inputs. It can work like a serializer though if we would select the input signals one after another.

Multiplexers are also called:

  • mux

  • data selector

Exercise 81

  1. What does a multiplexer in the context of digital electronics do?

  2. Which interface signals does a multiplexer have?

Exercise 82

Why does a multiplexer have \(\log_2 N\) select input signals where \(N\) is the number of input signals?

Exercise 83

What does a 16:1 mux mean?

Exercise 84

We introduced K-maps with entered variables before. How are these useful for describing the behavior of multiplexers?


The author writes

An N-input mux is a simple SOP circuit constructed from N AND gates each with log2N+1 …

It is actually \(\log_2 N +1\)

Exercise 85

Which and how many gates do we need for a multiplexer with 16 inputs and 4 select inputs?

Exercise 86

Assume that you have only 4:1 muxes. How many of these would you need to multiplex eight signals which are four bytes each?

Exercise 87

What is an application of multiplexers in computers?

Binary Decoders, Demultiplexers#

Binary Decoders#

Exercise 88

What does a binary decoder do? Give an example.

Exercise 89

Where can decoders be used in computing?

Exercise 90

How can we describe a decoder using a K-map?


Exercise 91

  1. What does a demultiplexer in the context of digital electronics do?

  2. Which interface signals does a demultiplexer have?

Exercise 92

How can we build a demultiplexer using a binary decoder?

Priority Encoders#

Exercise 93

  1. What is an encoder in the context of digital electronics?

  2. What is the difference between an encoder and priority encoder?

  3. Which interface signals does a priority encoder have?

Exercise 94

Why does a priority encoder exist but not a priority decoder?

Exercise 95

How can we describe a priority decoder using a K-map?


Exercise 96

  1. What does a shifter in the context of digital electronics do?

  2. Which interface signals does a shifter have?

Exercise 97

How does a truth table for a four input shifter with enable and without a fill bit look like?

Exercise 98

Where are shifters used?

Tutorial: Multiplexer, Shifter, Encoder, Decoder#

Exercise 99

How can we describe a 4:1 multiplexer in Systemverilog?

Exercise 100

  1. Describe a shifter with:

    • eight bit input

    • direction select

    • two bit shift count.

  2. Add a fill bit input to the shifter above.


1. Multiplexer#


You must also simulate the circuit.

In next weeks the circuits will become more complex and debugging your circuit using simulation can

  1. save you the time for synthesis

  2. give you a better insight to the internal signals

So getting to grips with simulation right now can be beneficial.

2. Decoder#

3. Encoder#

A priority encoder is required. A priority decoder can be implemented with if ... else statements that check the conditions in sequence and thus prioritize the first conditions when deciding what to output.

Can it also be implemented using a case statement? Does case check the conditions in sequence or in parallel? Instead of doing an internet search we can look to the standard document for Verilog which acts like the law book for the syntax and resulting semantics. It is also called language reference manual.

IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language

The standard is not free, but you can very likely download it using the subscription of your university or company.

case statement is explained in chapter 12.5:

… The case_item_expressions shall be evaluated and then compared in the exact order in which they appear. … During the linear search, if one of the case_item_expressions matches the case_expression, then the statement associated with that case_item shall be executed, and the linear search shall terminate. …

We can read that the case statement should behave like an if ... else and thus like a priority encoder.

What if we wanted to check in parallel? For example if we want to implement a multiplexer? For that the Verilog supplies unique case`:

unique-case … assert(s) that there are no overlapping case_items and hence that it is safe for the case_items to be evaluated in parallel. …

… The case_item_expressions may be evaluated in any order and compared in any order …

… By specifying unique or priority, it is not necessary to code a default case to trap unexpected case values. …

So if we want to be more explicit, then we would use unique case statement for a multiplexer.

4. Shifter#