Problem Set 6

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Problem Set 6#

Source: DL_P6_Probset.pdf Revision: n/a

1#

Complete a timing diagram to show how a glitch might form in the SOP circuit below. Note the pairs dotted lines in the timing diagram – you should show signal changes on the left line (labeled ‘1’), and assume the time between the dotted lines is the delay for ALL gates (not just the inverter). You don’t need to use all the dotted lines – just use enough of the timing diagram to clearly show the glitch.

assign F = (A | B) & (~B | C)

How can we cause a glitch?

Start A, B, C at low-level and transition B from low-level to high-level later. This way the high-level of B will propagate and use the output of ~B|C which is at 1 to create a temporary 1:

Would we also get a glitch when we transition B from high-level to low-level?

If B is high, then the output is low. When we set B to low, then the fast path will cause a 0 in the upper input of OR while the second input is at 0 before it rises up to 1. So the output will stay at 0 and won’t show a glitch.:

We see that the presence of a glitch also depends on if the glitch causing signal has a rising or falling edge.

2#

The circuit above is copied below – sketch a modification to the circuit below to demonstrate how the potential for a glitch can be removed.

Using K-map:

So we have to introduce A|C as an additional gate and connect it to the AND. Inputting A|C additionally to the AND will avoid the glitch because the change of ~B|C does not have an effect now on the AND.

Another (off-script) solution would be to balance the delay on the B and ~B paths by introducing a delay element (for example two small inverters) on B.

3#

Complete a timing diagram to show how a glitch might form in the POS circuit below. As before, show signal changes on the left line (labeled ‘1’), and assume the time between the dotted lines is the delay for ALL gates (not just the inverter). You don’t need to use all the dotted lines – just use enough of the timing diagram to clearly show the glitch.

assign F = (A & B) | (~B & C)

Start A, B, C at high-level and change B to low-level later, because the outputs of ANDs will change then.

4#

The circuit above is copied below – sketch a modification to the circuit below to demonstrate how the potential for a glitch can be removed.

B is the coupled variable. Analogous to problem 2 we should decouple it by introducing (A & C) as a minterm.

5#

Add any needed logic term(s) to the equations below to remove the possibility of a glitch.

5.1#

assign X = (A & ~B) | (~A & C) | (B & ~C)

  • Between the first and second term A is coupled. Decouple using: ~B & C

  • Between the second and third term C is coupled. Decouple using: ~A & B

  • Between the first and third term B is coupled. Decouple using: A & ~C

5.2#

assign X = (~A | B) & (A | ~C) & (~B | C)

  • Between the first and second term A is coupled. Decouple using: B | ~C

  • Between the second and third term C is coupled. Decouple using: A | ~B

  • Between the first and third term B is coupled. Decouple using: ~A | C

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