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Chapter discussions:

Boolean Board Digital Logic Course
A First Project for the Boolean Board
Basic Logic Circuits
Combinational Logic Circuits
Basic Combinational Building Blocks
Structural Verilog for Combinational Circuits
Delays in Logic Circuits
Flip-Flops and Latches
Counters, Clock Dividers and the 7-segment Display
Adders, Multipliers and Comparators
A simple ALU
Introduction to state machines

Problem set solutions:

Problem Set 1
Problem Set 2
Problem Set 3
Problem Set 4
Problem Set 5
Problem Set 6
Problem Set 7
Problem Set 8
Problem Set 9
Problem Set 10
Problem Set 11

Examples

Simulation using Verilator + GtkWave
State machine example
ADC reading
Display output

Unsorted

The history of FPGA
FPGA infrastructure
SystemVerilog guide
Questions from students
Credits and license

.md

Problem Set 4

Contents

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- Page 3
- Page 4

Problem Set 4#

Source: DigitalLogic_P4.pdf Revision: not available

Page 1#

handwritten solution

Page 2#

handwritten solution

Page 3#

handwritten solution

Page 4#

handwritten solution

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Problem Set 3

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Problem Set 5

Contents

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By Gökçe Aydos

Last updated on 19 Jul 2024.