Problem Set 7

Source: DL_P7_Problem_Set_9_28_18.pdf Revision: n/a

1

Sketch circuits for the NAND and NOR basic cells for the SR latch, and label the S and R inputs and Q output (and be sure the output Q comes from the proper gate – either the gate driven by Set or the gate driven by reset – it will only work properly if Q comes from the right gate). Then sketch their respective block diagrams (being sure to show bubbles on inputs that are asserted low), and complete the truth tables to document their operation.

1. NOR-based cell

   1. circuit diagram

   2. block diagram

   3. truth table

2. NAND-based cell

   1. circuit diagram

   2. block diagram

   3. truth table

---

1. NOR-based cell:

   2. 

   3. S	R	Q
      0	0	hold
      0	1	0
      1	0	1
      1	1	0

      If S and R are both active (1), then both NORs will output 0.

2. NAND-based cell:

   2. 

   3. S	R	Q
      0	0	1
      0	1	1
      1	0	0
      1	1	hold

      If S and R are both active (0), then both NANDs will output 1.

For detailed building instructions refer to Exercise 119.

2

Sketch the circuit for a D latch based on a NAND basic cell, and then sketch a timing diagram visualizing the D, E and Q signals to illustrate its function. Be sure to illustrate all the important states in your timing diagram (hint: there are four).

---

For detailed building instructions refer to Exercise 123.

Important states:

• reset: \(D=0\), \(E=1\)

• set: \(D=1\), \(E=1\)

• hold:

  • \(D=0\), \(E=0\)

  • \(D=1\), \(E=0\)

3

Complete the timing diagrams to document the behavior of

1. a D-latch with reset (output Q1)

2. a D-flip-flop with reset (output Q2)

E_or_clk is the enable for the D-latch and the clock for the D flip-flop.

---

Why do we have an additional reset signal if we can already reset the flip-flops using D and E?

Using reset we can reset the D-latch and flip-flop unconditionally, in other words we can reset regardless of the E or clock signal.

Compared to the level-triggered D latch, the edge-triggered D flip-flop registers the values only at the rising edge.

Note that the output can glitch dependent on the edge-triggered D flip-flop implementation and the transition of D when the clock is high. Refer to Exercise 124.

4

Complete the timing diagram to show the time course for circuit nodes A, B, C, and F1.

---

This is a group of flip-flops which are dancing to the same beat. They have the same clock and cascaded. This is a shift register where the last two bits are input to a NAND and fed back.

How do we draw the signals?

The reset signal resets every flip-flop, so F1 is 1 before the first clock cycle (and thus the first shift operation).

1. B depends on the previous value of A (thus F1)

2. C depends on the previous value of B

3. F1 depends on the current value of C and the previous value of C

4. A and F1 are connected, so we can get the current value of A

We can use the steps above in order the draw the waveforms.

5

Simulate the following sequence shown in the table below (Requirement 3 in Project 7: SR-Latches and D-Latch) and fill out the table below by writing the corresponding letters to empty columns based on your simulation.

A. Set operation B. Reset operation C. Confounded outputs (both outputs at the same voltage) D. Storing a value in memory E. A metastable state

Time	Set	Reset	NAND Cell	NOR Cell
100ns	1→0	1→1
200ns	0→1	1→0
300ns	1→1	0→1
400ns	1→0	1→0
500ns	0→1	0→1
600ns	1→0	1→0
700ns	0→0	0→1
800ns	0→1	1→0

Note

The text

(Requirement 3 in Project 7: SR-Latches and D-Latch) is misleading. The exercise probably asks for the analysis of NAND and NOR-based SR latches.

---

SR latch is driven to a metastable state if we issue a set or reset operation before the opposite operation is complete.

The following table shows what happens at the given time point.

Time	Set	Reset	NAND Cell	NOR Cell
100ns	1→0	1→1	Set op. (was storing value)	Reset op. (was confounded o.)
200ns	0→1	1→0	Reset op.	Set op.
300ns	1→1	0→1	Store value	Confounded o.
400ns	1→0	1→0	Confounded o.	Metastable
500ns	0→1	0→1	Metastable	Confounded o.
600ns	1→0	1→0	Confounded o.	Metastable
700ns	0→0	0→1	Set op.	Reset op.
800ns	0→1	1→0	Reset op.	Set op.