Problem Set 5

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Problem Set 5#

Source: DL_P5_Probset.pdf Revision: 2/3/19

1#

Complete Verilog code for a multiplexer-based circuit that performs according to the circuit sketch below.

module P1 (
	input A, B, C, D,
	output Y);

assign Y =

endmodule

Using minterms:

module P1 (
	input A, B, C, D,
	output Y);

assign Y =
	(A ~& B) & (~C & ~D) |
	(~A | ~B) & (~C & D) |
	(~A & B) & (C & ~D) |
	(A ^ B) & (C & D);

endmodule

Using ternary ?: operator:

module P1 (
	input A, B, C, D,
	output Y);

assign Y =
	C ? (
		D ? (A ^ B) : (~A & B)
	) : (
		D ? (~A | ~B) : (A ~& B)
	);
endmodule

A more readable approach compared to the last solution by making the structures (gates and the mux) more clear:

module P1 (
	input A, B, C, D,
	output Y);

wire [3:0] i;
wire [1:0] s;

assign s[0] = D;
assign s[1] = C;

assign i[0] = (A ~& B);
assign i[1] = (~A | ~B);
assign i[2] = (~A & B);
assign i[3] = (A ^ B);

assign Y =
	(s == 2'b00) ? i[0] : (
		(s == 2'b01) ? i[1] : (
			(s == 2'b10) ? i[2] :
				i[3]
		)
	);
endmodule

Note that a behavioral description using case statement would lead to more readable code, but the solution must be based on an assign statement.

2#

Complete Verilog code to define a circuit that implements the minterm equation:

\( F = \sum m(0, 2, 4, 5, 6) \)

module P2 (
	input
	output F);

assign F =

endmodule

Without minimizing the circuit and leaving the minimization to the compiler:

module P2 (
	input A, B, C,
	output F);

assign F =
	(~A & ~B & ~C) | // m0
	(~A & B & ~C) |  // m2
	(A & ~B & ~C) |  // m4
	(A & ~B & C) |   // m5
	(A & B & ~C);    // m6

endmodule

3#

Complete Verilog code to define the circuit shown.

module P3 (
	input A, B, C,
	output Y);

assign Y =

endmodule

module P3 (
	input A, B, C,
	output Y);

assign Y =
	~(
		~(~A & B)
	) |
	~(
		~(B & C)
	);

endmodule

4#

Compete Verilog code to define a 3:8 decoder. Include all required Verilog statements, including the module and endmodule statements.

Using minterms (and thus choosing a more structural approach using only gates) leads to an unreadable code:

module decoder_3to8 (
	input [2:0] i,
	output [7:0] o);

assign o[0] = ~i[2] & ~i[1] & ~i[0];
assign o[1] = ~i[2] & ~i[1] &  i[0];
assign o[2] = ~i[2] &  i[1] & ~i[0];
assign o[3] = ~i[2] &  i[1] &  i[0];
assign o[4] =  i[2] & ~i[1] & ~i[0];
assign o[5] =  i[2] & ~i[1] &  i[0];
assign o[6] =  i[2] &  i[1] & ~i[0];
assign o[7] =  i[2] &  i[1] &  i[0];

endmodule

A more readable approach is a behavioral description:

module decoder_3to8 (
	input [2:0] i,
	output reg [7:0] o);

always @ (i)
begin
	case (i)
		3'd0: o = 8'b0000_0001;
		3'd1: o = 8'b0000_0010;
		3'd2: o = 8'b0000_0100;
		3'd3: o = 8'b0000_1000;
		3'd4: o = 8'b0001_0000;
		3'd5: o = 8'b0010_0000;
		3'd6: o = 8'b0100_0000;
		3'd7: o = 8'b1000_0000;
	endcase
end
endmodule

A more readable and minimal approach:

module decoder_3to8 (
	input [2:0] i,
	output [7:0] o);

assign o = 1 << i;

endmodule

For other approaches, refer to B.Baas – decoder design examples

5#

Complete Verilog code to define a circuit that can shift an 8-bit input data value “D” left or right by up to three bits as defined by the 2-bit “A” input, and drive an output bus “R” with the result (note: if A is ‘00’, then the data simply passes through).

module P5 (
	input [7:0] D, LnR, [1:0] A,
	output [7:0] R);

assign R =

endmodule

Using ?:

module P5 (
	input [7:0] D, LnR, [1:0] A,
	output [7:0] R);

assign R = LnR ? D >> A : D << A;

endmodule

Using case:

module P5 (
	input [7:0] D,  // Data input
	LnR,            // Shift right if high
	input [1:0] A,  // Shift amount
	output [7:0] R);

reg [7:0] R_reg;

always @(*) begin
	case(LnR)
	0: R_reg = D << A;
	1: R_reg = D >> A;
	endcase	
end

assign R = R_reg;

endmodule
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