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Chapter discussions:

Boolean Board Digital Logic Course
A First Project for the Boolean Board
Basic Logic Circuits
Combinational Logic Circuits
Basic Combinational Building Blocks
Structural Verilog for Combinational Circuits
Delays in Logic Circuits
Flip-Flops and Latches
Counters, Clock Dividers and the 7-segment Display
Adders, Multipliers and Comparators
A simple ALU
Introduction to state machines

Problem set solutions:

Problem Set 1
Problem Set 2
Problem Set 3
Problem Set 4
Problem Set 5
Problem Set 6
Problem Set 7
Problem Set 8
Problem Set 9
Problem Set 10
Problem Set 11

Examples

Simulation using Verilator + GtkWave
State machine example
ADC reading
Display output

Unsorted

The history of FPGA
FPGA infrastructure
SystemVerilog guide
Questions from students
Credits and license

.md

Problem Set 3

Problem Set 3#

Source: DL_P3.pdf Revision: 2/3/19

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Problem Set 2

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Problem Set 4

By Gökçe Aydos

Last updated on 19 Jul 2024.